1. Field of the Invention
This invention relates generally to a dynamic random access memory with self-refresh function and particularly to a system and a method for reducing the consumption power of such a dynamic random access memory. More particularly, this invention relates to the construction of a substrate bias generating circuit and a method of generating a bias voltage, by which the necessary substrate bias potential can be generated with a minimum of consumption power on the refresh mode.
2. Brief Description of the Background Art
Recent years have seen a remarkable spread in the use of personal computers in a broad range of applications. among such personal computers, portable models in particular are in great demand, and for use in such portable personal computers, a low-power-consuming memory device with battery backup mode is being demanded.
As such a memory device, usually a dynamic random access memory (DRAM) or a static random access memory (SRAM) has been employed. Of these devices, the DRAM operates on the principle of accumulating the information charge in a MOS capacitor (a capacitor comprising a metal layer as an electrode, a semiconductor layer as the other electrode and an interlayer layer insulating film as a dielectric layer). However, in the MOS capacitor, the accumulated charge is gradually lost due to leaks across the junction between the semiconductor region, which serves as said other electrode, and the semiconductor substrate, thus making it necessary to rewrite the stored information at timed intervals. Such a rewriting action is known as refreshing. When a DRAM is used as the memory of a portable personal computer, it is necessary to perform refreshing at timed intervals even on a battery backup mode.
The general refresh modes for the DRAM are RAS0 only refresh and CAS0 before RAS0 refresh. The RAS0 only refresh is the refresh mode in which an external row address for refresh (refresh address) is applied and the level of row address strobe signal RAS0 is lowered to bring the DRAM into a selectable state. In this RAS0 only refresh, the column address strobe signal CAS0 is held at "H" level. The CAS0 before RAS0 refresh is the refresh mode in which, before the level of signal RAS0 is decreased to "L" level, the signal CAS0 is first decreased to "L" level so that a refresh instruction signal is issued to let an automatic refresh proceed according to the state of this signal. On whichever of these general refresh modes, refreshing is executed under the cycle-by-cycle control of external clocks such as the signals RAS0 and CAS Therefore, the use of such general refresh mode during battery backup would call for complicate control which is undesirable.
To overcome the above disadvantage there has been proposed and put to use a DRAM with an implementation enabling a refresh of stored data to be easily performed even in the battery backup mode. This DRAM has, a refresh address and a timer circuit for designating the timing of refresh for each row and has a self-refresh function such that refreshes are automatically executed under the control of the timer circuit. While the above DRAM with self-refresh function has been described in detail by Yamada et al. in "A 64K bit MOS Dynamic RAM with Auto/Self Refresh Functions," The Transactions of the Institute of Electronics and Communication Engineers, Japan, Vol, J66-C No. 1, January 1983, pp 62-69", a brief overview of the DRAM is presented below.
FIG. 1 is a block diagram showing a typical construction of the conventional 64K bit DRAM with self-refresh function. In this figure, only the elements and components relevant to refresh action are shown. Referring to FIG. 1, the DRAM comprises a memory array 97 including memory cells arranged in 256 (2.sup.8) rows x 256 (2.sup.8) columns, an address buffer 96 which receives an address signal from an address multiplexer 95, holds it temporarily and generates an internal row address signal, and a row decoder 98 which, in response to the internal row address signal from the address buffer 96, selects the corresponding one row out of the memory array 97. The address buffer 96 supplies a 7-bit internal address signal RA0-RA6 to the row decoder 98. Though not shown in detail, the memory array 97 is divided into two blocks of 128 rows x 256 columns each, and from these two blocks, two word lines are simultaneously selected by the signal RA0-RA6, that is, one word line from each block. The most significant address signal RA7 from the address buffer 96 is used as a block selection address signal.
The address multiplexer 95 receives a row address signal A0-A7 from an external device and a refresh Q0-Q6 from a refresh address counter 94 and feeds either one of these signals to the address buffer 96 under the control of a refresh controller 92. As the external address signal A0-A7, a row address signal and a column address signal are subjected to time-divisional multiplexing and supplied to the address multiplexer 95.
For the purpose of designating the refresh mode of the DRAM, the memory further includes a self-refresh mode detector 91 which receives a signal REF0 via an input terminal 1 and detects whether there exists a designation of the self-refresh mode and refresh controller 92 which, in response to an output of a self-refresh mode detector 91, generates signals for controlling the actions of the address multiplexer 95, refresh address counter 94 and timer 93. The address multiplexer 95, in response to a refresh instruction signal from the refresh controller 92, supplies a refresh address Q0-Q6 from the refresh address counter 94 to the address buffer 96.
The timer 93, in response to the refresh instruction signal .phi..sub.T from the refresh controller 92, outputs a refresh mode enable signal .phi..sub.R at a predetermined interval. The refresh address counter 94, in response to the refresh enable signal .phi..sub.R from the timer 93, increments its count and supplies the address multiplexer 95 with the refresh address Q0-Q6 corresponding to the count under the control of the refresh controller 92. The action of the DRAM thus constructed is briefly explained below.
The signal RAS0 fed to an input terminal 2 is held at "H" level (standby state) and the external refresh signal REF0 fed to the input terminal 1 is set to "L" level. In response to this state, the self-refresh mode detector 91 detects that a refresh is instructed and accordingly outputs a refresh instruction signal .phi..sub.S. In response to this refresh instruction signal .phi..sub.S, the address multiplexer 95 supplies a refresh address Q0-Q6 from the refresh address counter 94 to the address buffer 96 under the control of the refresh controller 92. The address buffer 96 generates an internal refresh address signal RA0-RA6 from the refresh address Q0-Q6 and supplies it to the row decoder 98. The row decoder 98 decodes this 7-bit refresh address Q0-Q6 and selects one row out of the 128 rows in each block of the memory array 97. Then, a refresh of data is carried out in the memory cells connected to the selected row in a usual manner.
When the external refresh signal REF0 remains at "L" level for more than a preset time (16 .mu.s at maximum), the designation of the self-refresh mode is detected by the self-refresh mode detector 91. In response to this detection of the designation of the self-refresh mode, the refresh controller 92 raises the level of signal .phi..sub.T to drive the timer 93. In response to this timer start signal .phi..sub.T, the timer 93 outputs a refresh enable signal .phi..sub.R upon lapse of the preset time (16 .mu.s maximum) to the refresh controller 92. In response to this refresh enable signal .phi..sub.R, the refresh controller 92 performs an incrementation of the count of the refresh address counter 94. In response, the refresh address counter 94 supplies the address multiplexer 95 with a refresh address Q0-Q6 different from the refresh address output in the previous refresh cycle. Similarly as in the previous refresh cycle, one row corresponding to this new refresh address Q0-Q6 is selected in the memory array 97 and the data in the memory cells connected to this newly selected roe is refreshed. The generation of refresh enable signal .phi..sub.R from the timer 93 is repeatedly carried out at a predetermined cycle as long as the external refresh signal REF0 remains at "L" level and the signal RAS0 at "H" level. Therefore, in each block of the memory array 97, 128 word lines are sequentially selected and the data in the memory cells connected to the respective selected word lines are refreshed. Taking a 64K bit DRAM as an example, all the memory cells in the memory array 97 are refreshed in 16 .mu.s x 128=about 2 ms. In the battery backup mode with the main power supply OFF, the signal REF0 is brought into a low level in response to the change of power supply, and the above refreshing is performed.
Usually, in the above-described DRAM, there is provided a substrate bias generator for reducing the parasitic capacitance between the DRAM circuit elements and the semiconductor substrate supporting the DRAM to assure a high-speed and a stable action of the DRAM. Thus, for the purpose of reducing the junction capacitance between the semiconductor substrate and the impurity region (source drain regions), stabilizing the threshold voltage of the MOS transistors formed on the semiconductor substrate, and inhibiting the generation of a parasitic MOS transistor comprising a signal line layer on the field insulation film and the impurity region on the surface of the semiconductor substrate, the semiconductor substrate is biased to a negative potential V.sub.BB, in the case of p type substrate.
FIG. 2 shows an example of a conventional substrate bias generator for use in a DRAM with self-refresh function. Referring to FIG. 2, the substrate bias generator indicated generally at 41 comprises a ring oscillator 411 which outputs an oscillation signal .phi..sub.CP of predetermined frequency, a charge pump capacitor C which receives this oscillation signal from ring oscillator 411, an n-channel MOS transistor Ql interposed between a node N.sub.B and the ground potential and adapted to clamp the potential of node N.sub.B at its threshold voltage level, and an n-channel MOS transistor Q2 interposed between the node N.sub.B and an output terminal 412 and adapted to clamp the node N.sub.B at a potential level which is determined by the difference between its threshold voltage and the potential of the semiconductor substrate.
FIG. 3 shows waveforms explaining the action of the substrate bias generator illustrated in FIG. 2. The operation of the substrate bias generator is briefly described below with reference to FIGS. 2 and 3.
When the oscillation signal .phi..sub.CP from the ring oscillator 411 is raised to "H" level, the potential of node N.sub.B tends to rise to "H" level, which is the supply potential level V.sub.CC, due to capacitive coupling through the capacitor C. In response to this increase at node N.sub.B in potential, the MOS transistor Q1 becomes conductive and the potential at this node N.sub.B is clamped at the threshold voltage level V.sub.VT1 of MOS transistor Q1, In this stage, the MOS transistor Q22 remains OFF.
Then, as the oscillation signal .phi..sub.CP falls to "L" level, the potential at node N.sub.B is also decreased by capacitive coupling of the capacitor C. In response to this decrease in potential at node N.sub.B, the MOS transistor Ql becomes OFF while the MOS transistor Q2 is turned ON, with the result that a positive charge flows from the semiconductor substrate to node N.sub.B. When this potential at node N.sub.B reaches a value equal to the difference between the semiconductor substrate potential V.sub.BB and the threshold voltage V.sub.T2 of MOS transistor Q2, the MOS transistor Q2 becomes non-conductive so that the movement of the charge is stopped. By this one cycle of the rise and fall of oscillation signal .phi..sub.CP, the potential of the semiconductor substrate is decreased only a little. However, as the same cycle is repeated many times, the semiconductor substrate voltage V.sub.BB decreases by degrees until a certain negative potential is established. With the supply voltage being V.sub.CC, the bias voltage V.sub.BB of this semiconductor substrate is V.sub.T1 +V.sub.T2 -V.sub.CC under ideal conditions and is generally a value of about -3V.
It will be apparent from the above description that in the conventional dynamic random access memory, the substrate bias generator is constantly functioning and consuming the same power, whether in the normal operating mode or in the self-refresh mode.
However, in the self-refresh mode, other actions than refreshing, such as data write/read and column selection are not performed. Therefore, the substrate leak current flowing into the semiconductor substrate (the hole current generated in circuit operation) is smaller in the self-refresh mode than in the normal operating mode and, moreover, the amount of leakage current in the self-refresh mode is predictable. Therefore, the power consumption is minimized during the self-refresh mode, or the battery backup operation. The conventional DRAM, however, has the drawback that the substrate bias generator consumes as much power during the self-refresh mode as in the normal operation or refresh mode.
Furthermore, Japanese Pat. Publication KOKAI No. 59688/1986 discloses the RAM construction including a pair of substrate bias generators having different biasing capacities, with the substrate bias generator with the larger biasing capacity being driven in the self-refresh mode. However, in this construction, too, the substrate bias generator with the larger biasing capacity is continuously driven during the refresh mode, thus entailing an unnecessary power consumption.
A still another DRAM with self-refresh function has been proposed by Taniguchi et al., "Fully Boosted 64K Dynamic RAM with Automatic and Self-Refresh", IEEE Journal of Solid-State Circuits, Vol. SC-16, No. 5, October 1981, pp. 492-498. This literature contains no discussion on the subject of power dissipation of the substrate bias generator.